Post by Kent Hansenhttps://groups.google.com/forum/#!topic/fameisfame/YR6f8pA7jYc has a
recent status.
"The team doing the MIPS port] are not part of V8 team but they are
contributing their code back to main V8 repo. [...] Our main repo AFAIK
is still behind theirs in terms of MIPS support (e.g. optimizing
compiler is not yet merged)."
That's good to know. It would be interesting to know as well how well the
simulators work on other 32-bit platforms, including each other. The easiest
access we have is to run the MIPS simulator on ARM.
I looked at the ARM code yesterday extensively and, aside from one very poor
programming practice in the source code, I don't see anything that would
prevent it from working.
The poor programming practice I found is the casting of function pointers to
different types of function pointers.
Post by Kent HansenQtCore doesn't depend on V8 yet. Sure, that might be the direction we
want to go, but it doesn't do it _yet_.
I'm sorry about the (unannounced) breakage of Qt Base. I'll be doing
what I can to ensure that V8 stays "out of the way" for those who don't
need it / can't build it. Step one should be working now (when -no-v8 is
given, don't build it!); step two would be configure-time detection, as
you suggested.
I know, thanks for your effort.
The reason I posted the email was because I had discussed with Lars the
possibility of using V8 in QtCore. My initial investigations have shown me
that V8 is currently not acceptable for QtCore and it will not become
acceptable by the feature freeze time.
For that reason, I recommend evaluating alternatives to QRegExp's replacement,
like using PCRE.
Note how V8 had been in use in QtDeclarative for some time and I didn't
complain. It's only when it became close to be used in QtCore that I decided
to investigate some more.
Post by Kent HansenConfirmed, see Thiago's later mail. Some pointers (e.g. callbacks) that
you pass through the public API are written straight to fields of JS
heap objects, and there's no provision for host pointer size being
different from target pointer size, it seems.
Regarding performance of the ARM simulator: Compared to a native build,
the slowdown on ia32 is about 150x on average for the V8 benchmarks (as
much as 250x for one, down to 15x for another).
As I said, the simulator is not meant to be used in production. It's only
meant to be used to debug the generated code and the compiler, without having
to debug on-device. It also simulates the cache functionality, by maintaining
a cache line state -- this is probably causing a major slowdown.
I spent a great deal of time yesterday trying to "invent ARM64". I managed to
modify assembler-arm.h enough to be 64-bit safe and I added an ldrptr/strptr
pair that would emit 64-bit loads and stores on 64-bit. I also managed to get
the simulator to build in 64-bit mode, using MIPS64 semantics -- registers are
64-bit in size and operations on 32-bit sign-extend to 64-bit.
Then I started looking at the code generators. To port it to 64-bit, this will
require reading everything, line by line, and decide at every "ldr" or "str"
call to see if the object being managed is an int or a pointer-sized object.
Comparing to the x86-64 equivalent helps, but isn't always obvious.
If we were to make "ARM64" or even MIPS64, it needs to be done in cooperation
with upstream, or maintainance would be an incredible nightmare.
For that reason, a p-code architecture or simple AST-runner would be
preferable, even if we can't get the benefits of an optimising compiler. I
haven't investigated the complexity of doing this, aside from seeing that each
of the three major architectures is 40k lines of code.
TBH, a generic runner might have some benefits for the project as a whole. I
can't see right now what the reference implementation is and how to validate
that the assembly is doing what it's supposed to do.
--
Thiago Macieira - thiago (AT) macieira.info - thiago (AT) kde.org
Software Architect - Intel Open Source Technology Center
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